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Computer System Architecture

Lecture Notes

 

SES #

TOPICS

Module 1

L1

History of Calculation and Computer Architecture (A) (PDF)

L2

Influence of Technology and Software on Instruction Sets: Up to the dawn of IBM 360 (A) (PDF)

L3

Complex Instruction Set Evolution in the Sixties: Stack and GPR Architectures (A) (PDF)

L4

Microprogramming (A) (PDF)

L5

Simple Instruction Pipelining (A) (PDF)

L6

Pipeline Hazards (A) (PDF)

Module 2

L7

Multilevel Memories - Technology (J) (PDF)

L8

Cache (Memory) Performance Optimization (J) (PDF)

L9

Virtual Memory Basics (J) (PDF)

L10

Virtual Memory: Part Deux (A) (PDF)

Module 3

L11

Complex Pipelining (A) (PDF)

L12

Out of Order Execution and Register Renaming (A) (PDF)

L13

Branch Prediction and Speculative Execution (A) (PDF)

L14

Advanced Superscalar Architectures (J) (PDF)

L15

Microprocessor Evolution: 4004 to Pentium 4 (J) (PDF)

Module 4

L16

Synchronization and Sequential Consistency (A) (PDF)

L17

Cache Coherence (A) (PDF)

L18

Cache Coherence (Implementation) (A) (PDF)

L19

Snoopy Protocols (A) (PDF)

L20

Relaxed Memory Models (A) (PDF)

Module 5

L21

VLIW/EPIC: Statically Scheduled ILP (J) (PDF)

L22

Vector Computers (J) (PDF)

L23

Multithreaded Processors (J) (PDF)

L24

Reliable Architectures (J) (PDF)

L25

Virtual Machines (J) (PDF)

Assignments

This section contains the problem sets assigned for the course. Each of the problem sets is related to a module. Although problem solutions do not have to be handed in (and consequently, are not graded), it is essential that students become thoroughly familiar with the material and therefore are encouraged to work through all problems.

The self-assessment test was handed out during the first lecture and used to assess each student's preparation for the course. The test was due one week later in the lecture. The handouts were provided to students to assist them in completing the problem sets. Students were expected to study the handouts before solving the problems. Instructors may request the solutions for these assignments by using the MIT OpenCourseWarefeedback form.

ASSIGNMENTS

TOPICS

HANDOUTS

Problem Set 0

Prerequisite Self-Assessment Test (PDF)

 

Problem Set 1

ISAs, Microprogramming, Simple Pipelining and Hazards (PDF ‑ 3.6 MB)

Handout 1: EDSACjr (PDF)

Handout 2: 6.823 Stack ISA (PDF)

Handout 3: CISC ISA--x86jr (PDF)

Handout 4: RISC ISA--6.823 MIPS (PDF)

Handout 5: Bus-based MIPS Implementation (PDF)

Problem Set 2

Caches and Virtual Memory (PDF)

Handout 6: Cache Implementations (PDF)

Handout 7: Victim Cache (PDF)

Handout 8: Virtual Memory Implementation (PDF)

Problem Set 3

Complex Pipelines (PDF)

Handout 9: Scoreboarding (PDF)

Handout 10: Out-of-order Execution with ROB (PDF)

Handout 11: Physical Register Management (PDF)

Problem Set 4

SMPs, CC, Synch and Memory Models (PDF)

Handout 12: Directory-based Cache Coherence Protocol (PDF)

Handout 13: Snoopy Cache Coherence Protocol (PDF)

Problem Set 5

VLIW, Vector and Threads (PDF)

 

Exams

This section contains actual exams given to students throughout the course. Instructors may request the solutions for these assignments by using the MIT OpenCourseWare Feedback form.

Quiz 1 (PDF ‑ 1.5 MB)

Quiz 2 (PDF)

Quiz 3 (PDF)

Quiz 4 (PDF)

Quiz 5 (PDF)