Complex Digital Systems

Lecture Notes

The table below contains information on the course's lectures (L) and tutorials (T). Tutorials 1 and 2 are courtesy of Christopher Batten. Tutorial 3 is courtesy of Michael Pellauer.

LEC #

TOPICS

L1

Introduction (PDF - 1.7 MB)

L2

Digital Design Using Verilog (PDF)

L3

CMOS Technology and Logic Gates (PDF - 2.4 MB)

T1

Verilog Simulation I (PDF)

L4

Wires (PDF - 1.4 MB)

L5

Synthesis (PDF)

T2

Verilog Simulation II (PDF)

L6

Clocking (PDF)

L7

Bluespec I: Motivation (PDF)

L8

Bluespec II: Designing with Rules (PDF)

L9

Bluespec III: Modules and Interfaces (PDF)

L10

Bluespec IV: Rule Scheduling and Synthesis (PDF)

T3

Bluespec (PDF)

L11

Power (PDF)

L12

Bluespec V: Processors (PDF)

L13

Bluespec VI: Modularity and Performance (PDF)

L14

Transaction Level Design and Verification (PDF)

L15

Testing (PDF)

 

Labs

See the calendar for due dates and the syllabus for class policies on turning in labs and collaboration. The SMIPS Processor Specification contains details on the SMIPS ISA which is used in several of the labs.

LAB #

TOPICS

1

RTL Model of a Two-Stage MIPS Processor (PDF)

2

ASIC Implementation of a Two-Stage MIPS Processor (PDF)

3

Bluespec Model of a Network Linecard (PDF)

 

Exams

Quiz Study Guide (PDF)

Quiz without Solutions (PDF)

Quiz with Solutions (PDF)

Related Resources

Online Verilog HDL Quick Reference Guide: Very useful online reference for Verilog-1995. It won't have the newer Verilog-2001 constructs but it is still a very convenient way to look up 99% of what you need to know.

Verilog-2001: What's New: This white paper by Stuart Sutherland crystalizes the key differences between Verilog-1995 and Verlog-2001. (PDF)

Parameterized Models Using Verilog 2001: This white paper by Cliff Cummings clearly describes the evils of unnamed parameter instations and 'defines and shows how the new features in Verilog-2001 provide much safer ways to achieve the same effects. (PDF)