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    Calendar

    The first half of the class includes lectures on technology and scaling. In the second half of the course, students will work in small groups on large chip design projects with regular advisory meetings with the instructors.

    The calendar below provides information on the course's lecture (L), tutorial (T), quiz (Q), and project (P) sessions. The last lecture or recitation is delivered midway through the course; after that date, class time is spent entirely on group projects.

    ses # topics key dates

    L1

    Introduction

    L2

    Digital Design Using Verilog

    Lab 1 assigned

    L3

    CMOS Technology and Logic Gates

    T1

    Verilog Simulation I

    L4

    Wires

    L5

    Synthesis

    T2

    Verilog Simulation II

    L6

    Clocking

    Lab 1 due

    L7

    Bluespec I: Motivation

    Lab 2 assigned

    L8

    Bluespec II: Designing with Rules

    L9

    Bluespec III: Modules and Interfaces

    Lab 2 due

    L10

    Bluespec IV: Rule Scheduling and Synthesis

    T3

    Bluespec

    Lab 3 assigned

    L11

    Power

    Hand out project choices

    L12

    Bluespec V: Processors

    L13

    Bluespec VI: Modularity and Performance

    Lab 3 due

    L14

    Transaction Level Design and Verification

    L15

    Testing

    Q1

    Quiz

    Preliminary project proposals due

    P1

    Team Discussion on Preliminary Proposals (Groups 2, 3, 4)

    P2

    Team Discussion on Preliminary Proposals (Groups 1, 5, 6)

    Project proposals due 2 days after project session 2

    P3

    Team Discussion on UTL Design (Groups 2, 3, 6)

    P4

    Team Discussion on UTL Design (Groups 1, 4, 5)

    High-level UTL architectural doc due 2 days after project session 4

    P5

    Team Discussion on Test Strategy (Groups 2, 3, 6)

    P6

    Team Discussion on Test Strategy (Groups 1, 4, 5)

    Test strategy doc due 2 days after project session 6

    Ref impl working with test harness and in CVS

    P7

    Team Discussion on RTL (All Groups)

    Microarchitectural design doc due 2 days after project session 7

    Initial RTL design working and in CVS

    P8

    Team Discussion on Design Exploration (Groups 2, 3, 6)

    P9

    Team Discussion on Design Exploration (Groups 1, 4, 5)

    Design exploration doc due 2 days after project session 9

    Multiple alternative designs working and in CVS

    P10

    Final Team Discussion (Groups 2, 3, 6)

    P11

    Final Team Discussion (Groups 1, 4, 5)

    P12

    Project Presentations (Groups 2, 3, 6)

    P13

    Project Presentations (Groups 1, 4, 5)

    Final report due 2 days after project session 13