Lecture Notes
The table below contains information on the course's lectures (L) and tutorials (T). Tutorials 1 and 2 are courtesy of Christopher Batten. Tutorial 3 is courtesy of Michael Pellauer.
| Lec # | Topics |
|---|---|
| L1 | Introduction (PDF - 1.7 MB) |
| L2 | Digital Design Using Verilog (PDF) |
| L3 | CMOS Technology and Logic Gates (PDF - 2.4 MB) |
| T1 | Verilog Simulation I (PDF) |
| L4 | Wires (PDF - 1.4 MB) |
| L5 | Synthesis (PDF) |
| T2 | Verilog Simulation II (PDF) |
| L6 | Clocking (PDF) |
| L7 | Bluespec I: Motivation (PDF) |
| L8 | Bluespec II: Designing with Rules (PDF) |
| L9 | Bluespec III: Modules and Interfaces (PDF) |
| L10 | Bluespec IV: Rule Scheduling and Synthesis (PDF) |
| T3 | Bluespec (PDF) |
| L11 | Power (PDF) |
| L12 | Bluespec V: Processors (PDF) |
| L13 | Bluespec VI: Modularity and Performance (PDF) |
| L14 | Transaction Level Design and Verification (PDF) |
| L15 | Testing (PDF) |
